In the field of mobile communication, such as automobile telephone or portable telephone, an analog modulation system, represented by frequency modulation, has been conventionally employed. A digital modulation system has been recently utilized. Accompanying that change, production of an IC circuit for a quaternary modulator as a key device in the modulation section for performing multi-value digital modulation such as QPSK(quaternary phase shift keying) has been of increasing importance.
FIG. 21 is a diagram illustrating a transmitter and a receiver section of a portable telephone as an example of an apparatus using this quadrature modulator.
In FIG. 21, an audio signal converted to an analog signal by the phone receiver 221 is made a digital signal coded by the codec (CODEC) 220 in response to an instruction from the control section 219 and is output to the waveform generating circuit 218. The waveform generating circuit 218 is constituted by a DSP (digital signal processor) 218d, a ROM 218c, D/A converters 218a and 218b. In response to an instruction from the control section 219, it narrows the band of the digital signal input from the CODEC 220 by the DSP 218d, and decomposes the signal into I and Q signals, i.e., two signals having phases 90.degree. different from each other, using waveform data stored in the ROM 218c, and converts these signals to analog signals in the D/A converters 218a and 218b and outputs those analog signals to the quadrature modulator 216. The quadrature modulator 216 performs quadrature modulation of the analog I and Q signals output from the waveform generating circuit 218 using the local oscillator signal output from the frequency synthesizer 217. The quadrature modulated signal is up-converted to a radio frequency by the local oscillation signal output from the frequency synthesizer 215 at the modulator 214 to be output to the high output amplifier 213. The high output amplifier 213 amplifies the output signal of the modulator 214 to a high power output. The output of this amplifier 213 is output to the antenna 211 through the transmit and receive switch 224 to be radiated into space.
On the other hand, the antenna 211 and the antenna 212 constitute a so-called diversity antenna, and upon receipt of electromagnetic waves this diversity antenna supplies an input signal to the receiving part 222. The receiving part 222 amplifies the waves received by this diversity antenna and outputs the same to the demodulation section 223. The demodulation section 223 demodulates the output of the receiving section 222 and outputs the same to the CODEC 220. The CODEC 220 demodulates the digital signal demodulated by the demodulation section 223 to an audio signal and outputs the same to the phone receiver 221.
In this way, in the next generation portable telephone, i.e., so-called codeless telephone or an automobile telephone, a digital transmission system is employed. This digital transmission system does not modulate the frequency of the carrier with an audio signal as in FIG. 22(a), but modulates the phase of the carrier with the audio data as shown in FIG. 22(b).
In this digital transmission system, when phase information is carried on the carrier, the modulation is performed by using the values of (0, .pi./2, .pi., 3.pi./2) which are marked with white round mark .alpha. or the values of (.pi./4, 3.pi./4, 5.pi./4, 7.pi./4) which are marked with black round mark in FIG. 22(c), requiring a quadrature modulator.
FIG. 24 shows a block construction of a quadrature modulator including a 0.degree./90.degree. phase shifter In FIG. 24, reference numeral 1 designates an input buffer which performs waveform reforming of a signal input from the carrier wave input terminal Reference numeral 2 designates a 0.degree./90.degree. phase shifter for separating the signal wave reformed by the input buffer 1 into two signals having phases different by 90.degree.. Reference numeral 3 designates a buffer for wave reforming the output of the phase shifter 3. Reference numeral 4 designates a double balanced mixer which performs double balanced modulation of the base band signal as a signal to be modulated by the output of the buffer 3. The usual balanced mixer is only balanced to the carrier wave, and therefore, the signal to be modulated as well as the carrier wave do not appear at the output side, while a modulating signal such as an audio signal appears at the output side. On the other hand, the double balanced mixer is balanced to the carrier wave as well as to the modulated wave, and therefore only the signal to be modulated appears at the output, and neither of the carrier wave and the modulation wave appear at the output side. Further, reference character BB designates its base band signal input terminal, OUT designates an output signal terminal for the double balanced mixer 4, a, b, and c designate signal lines respectively connecting the input buffer 1 and the 0.degree./90.degree. phase shifter 2, the 0.degree./90.degree. phase shifter 2 and the buffer 3, and the buffer 3 and the double balanced mixer 4, respectively.
Next, a description is given of the operation.
The carrier wave signal input from the carrier wave input terminal IN is wave-reformed by the input buffer 1, and is output to the 0.degree./90.degree. phase shifter 2. In this 0.degree./90.degree. phase shifter 2, the input signal is separated into two series of signals which have phases shifted by 0.degree./90.degree. relative to the input signal, and they are output to the buffer 3. In the buffer 3, the wave-reforming of the input signal is performed in the same way as in the input buffer 1, and is output to the double balanced mixer 4. In the double balanced mixer 4, the base band signal input from the base band signal input terminal BB is used as a signal to be modulated to perform the double balanced modulation, thereby the modulated signal is output from the output signal terminal.
FIG. 23 is a diagram for explaining the operation of the quadrature modulator. In FIG. 23, the carrier wave input signal of cos .omega.t which is input to the 0.degree./90.degree. phase shifter 231 is converted to two signals by the 0.degree./90.degree. phase shifter 231 which are shifted in phase by 0.degree. and 90.degree., respectively, relative to the input signal of cos .omega.t, to be output to the double balanced mixers 232 and 233, respectively. In the double balanced mixers 232 and 233, the base band signals I(t) and Q(t) are respectively input as modulation signals and they are modulated by cos .omega.t and sin .omega.t, respectively, as output signals I(t)cos .omega.t and Q(t)sin .omega.t. These signals are input to the synthesizer circuit 234, thereby a quadrature modulated wave EQU e(t)=I(t)cos .omega.t+Q(t)sin .omega.t
is output.
Here, when it is supposed that I(t)=cos .phi.(t) and Q(t)=-sin .phi.(t), phase modulated waves are obtained as represented by, EQU e(t)=cos .phi.(t) : cos .omega.t-sin .phi.(t) : sin .omega.t=cos (.omega.t+.phi.(t)),
and when this .phi.(t) is given as 0, .pi./2, 3.pi./2, .pi., QPSK (quaternary phase shift keying) modulated wave is obtained.
Here, in this quadrature modulation, the balancing and the orthogonality of carriers, i.e., how close the phase difference is to 90.degree. affects the positions of the black round marks and white round marks in FIG. 22(c), and when the positions of these black round marks and white round marks in FIG. 22(c) are deviated, the quality of the modulation signal is reduced and demodulation is made difficult.
In other words, in the quadrature modulator, when the positions of the black marks and the white marks are deviated, there arises an image component of the modulation signal component, that is, an unrequited mirror image component. The mirror image component is deviated from the carrier wave by a frequency corresponding to the modulated signal, and in order to sufficiently suppress this image component, the preciseness of orthogonality of the carrier in the 0.degree./90.degree. phase shifter, that is, the phase difference of the carrier at precisely 0.degree. and 90.degree., respectively, is important.
The 0.degree./90.degree. phase shifter of such construction is conventionally constructed by using such as delay lines and microwave strip lines. However, there has been arising a necessity of realizing the 0.degree./90.degree. phase shifter also by a construction appropriate for circuit integration of a quadrature modulator in an integrated circuit. In order to realize a quadrature modulator superior in modulation characteristics, how a small-sized 0.degree./90.degree. phase shifter which is strong against variations of elements and appropriate for circuit integration, determines the performance of the IC and the yield thereof.
The phase shifter described in the following is an example of a conventional phase shifter circuit which requires no large chip area for an inductor and can be constructed of only resistors, capacitors, and transistors, and is appropriate for circuit integration.
FIG. 25 illustrates a phase shifter circuit which utilizes an all band pass type circuit as a conventional 0.degree./90.degree. phase shifter, and described in FIG. 1 of "Monolithic RC All-Pass Networks with Constant-Phase-Difference Outputs", on pp. 1533-1537 of "IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. MTT-34, NO. 12".
In FIG. 25, reference character IN1 designates a positive phase signal input terminal to which a positive phase signal of positive phase and negative phase input signals is applied, reference character IN2 designates a negative phase signal input terminal to which the negative phase signal having a phase shift of 180.degree. relative to said positive phase signal is input. Reference numeral V.sub.DD designates a power supply terminal, reference character V.sub.CS designates a constant current source bias terminal, and reference characters OUT1 and OUT2 designate output signal terminals. J1 and J2 designates a pair of differential FETs having the same gate widths, for example 30 .mu.m to 100 .mu.m, to which gates the positive phase signal and the negative phase signal are input, respectively. J3 designates a constant current FET having a drain connected to the commonly connected sources of the differential FETs J1 and J2, R3 designates a resistor connected between the source of the constant current FET J3 and the ground, R1 and R2 designate load resistors having the same resistance values, for example 1 to 3 k.OMEGA., connected between the drains of the differential FETs J1 and J2 and the power supply V.sub.DD.
Further, J4 and J6 designate source follower FETs having drains connected to the power supply terminals V.sub.DD and having gates connected to the terminals of the resistors R1 and R2 at the side opposite to the power supply terminal and which have the same gate widths. J5 and J7 designate constant current FETs having drains connected to the sources of the source follower FETs J4 and J6 and which have the same gate widths. R4 and R5 designate the constant current resistors having the same resistance values connected between the sources of the constant current FETs J5 and J7 and the ground, respectively. Here, the constant current FETs J5 and J7 are provided for increasing the impedance conversion effect due to the source follower FETs J4 and J6, that is, the effect of increasing the input impedance and decreasing the output impedance, and therefore these are not necessarily required. So, these can be omitted and the sources of FETs J4 and J6 may be directly connected to the resistors R4 and R6.
In addition, the FETs J3 to J7 all have gate widths of 50 .mu.m to 100 .mu.m and the resistors R3 to R5 all have resistance values of 200 .OMEGA. to 1 k.OMEGA..
In addition, reference characters Ra and Rb, and Ca and Cb designate resistors, and capacitances which together constitute the 0.degree./90.degree. phase shifter. The resistor Ra and the capacitor Ca are connected in series to each other and the resistor Rb and the capacitor Ca are connected in series to each other, and these two serially connected circuits 25a and 25b are connected between the sources of the source follower FETs J4 and J6, in parallel with each other. The output terminal OUT1 is taken out from the connection node between the resistor Ra and the capacitor Ca and the output terminal OUT2 is taken out from the connection node of the resistor Rb and the capacitor Cb. Reference numerals n4 and n6 designate source nodes of the source follower FETs J4, J6, respectively, and V1, V2 designate voltages of the nodes n4, n6, respectively, and Vout1 and Vout2 designate voltages of the output terminals OUT1 and OUT2, respectively.
In FIG. 25, a differential amplifier circuit 11a comprising the FETs J1, J2, J3 and resistors R1, R2, R3 is provided at a prior stage of the two source followers 11b and 11c comprising the FETs J4, J5 and the resistor R4, and the FETs J6, J7 and the resistor R5, respectively, is only illustrated as means for inputting signals having phases shifted by 180.degree. from each other to the FETs J4 and J6, respectively. The signals input to the input terminals IN1 and IN2 are not necessarily required to be of reverse phases, and either of the signal terminals can be made a reference of a constant voltage.
FIG. 26 is a diagram illustrating vectors of V1, V2(=-V1), and Vout1, Vout2 when the values of the resistors Ra, Rb, and the capacitors Ca, Cb constituting the 0.degree./90.degree. phase shifter 11d are set so that the Vout1 and Vout2 are made orthogonal to each other at the target frequency and .DELTA..phi. in the figure represents a phase difference between signals of the output voltages Vout1 and Vout2.
A description is given of the operation.
The signals input from the input terminals IN1 and IN2 are amplified by the differential amplifiers 11a, the differential outputs thereof are impedance converted to low impedances by the source follower circuit 11b and 11c, respectively, and are output to the 0.degree./90.degree. phase shifter 11d. In this phase shifter 11d, the resistance values of the resistors Ra and Rb and the capacitance values of the capacitors Ca and Cb are set so that two signals having phases orthogonal to each other at a specific frequency are output from the two outputs Vout1 and Vout2, respectively.
From FIG. 26, because the 0.degree./90.degree. phase shifter is of all-band pass type, when, for example, the center frequency is 250 MHz, the amplitudes of Vout1 and Vout2 are equal to the amplitudes of V1 and V2 over a wide band of 180 to 340 MHz, and the Vout1 and Vout 2 are represented as moving on an arc of a circle with diameters of V1 and V2 because the vectors of voltages RaIa and Ia/j.omega.Ca arising at the both ends of the resistors Ra and Rb and the capacitors Ca and Cb, respectively, are orthogonal to each other, and also the vectors RbIb and Ib/j.omega.Cb are mutually orthogonal to each other. Therefore, by setting the values of the resistances Ra, Rb, and the capacitances Ca, Cb, it is possible to output signals having phases deviated by 90.degree. from each other from the output terminals Vout1, Vout2, so that the phase difference .DELTA..phi. produced by Vout1 and Vout2 be 90.degree..
That is, in this 0.degree./90.degree. phase shifter, the voltage vectors Vout1 and Vout2 move on the arc of the circle with the originating point O of the voltage vectors V1 and V2(=-N1), and the triangle .DELTA.1 with the voltage vectors Vout1 and V1 and the triangle .DELTA.2 with the voltage vectors Vout2 and V2 become isosceles triangles. Here, when the Ra, Ca, Rb, Cb are set such that 1/.omega.Ca.multidot.tan 22.5.degree.=Ra and Rb.multidot.tan 22.5.degree.=1/.omega.Cb(.omega.=2.pi. fO : fO is a target frequency), because the angles .phi.1, .phi.2 become 22.5.degree., the .phi.21 produced by the voltage vector V1 and the Vout2 and the angle .phi.12 produced by the voltage vector V2 and the Vout1 become 45.degree.. Thereby, the angle .DELTA..phi. produced by the voltage vector Vout1 and the Vout2 are made 90.degree. and the phases of the output signals Vout1 and Vout2 are made orthogonal to each other.
Even without employing such a setting, by only appropriately setting the resistance values of the resistors Ra and Rb and the capacitance values of Ca and Cb appropriately, the output signals Vout1 and Vout2 can be made orthogonal to each other. This can be accomplished, for example, by setting the values as Ra=650 .OMEGA., Ca=0.6 p F, Rb=280 .OMEGA., Cb=0.25 pF, at frequency fO=950 MHz.
However, in this phase shifter, the Vout1 and Vout2 are generated by two serial connection circuits 25a and 25b, and the current paths generating the Vout1 and Vout2 are provided separately, the frequency band that can maintain a phase shift difference of 90.degree. cannot be made so wide, and, for example, when the center frequency is 250 MHz, the range in which the phase difference of 90.degree. can be maintained is limited to the vicinity of that frequency. In addition, the accuracy of the orthogonality of the separated signals into 0.degree. signal and 90.degree. signal components as a function of variations in the element characteristics in the resistors Ra and Rb and the capacitors Ca and Cb when the circuit is integrated is low.
FIG. 27 is a diagram illustrating an example of a phase shifter according to the prior art that can solve such a problem. In this circuit, by constituting a 0.degree./90.degree. phase shifter of differential circuits and integrating circuits, the problem of low accuracy of the orthogonality as a function of element variations in the circuit of FIG. 25 can be solved.
In FIG. 27, reference character IN designates a single signal input terminal, reference characters J11 and J13 designate source follower circuits which receive the input signal from the signal input terminal at their gates. The gate widths of the source follower FETs are equal to each other and the drains thereof are both connected to the power supply terminal V.sub.DD. J12 and J14 are constant current source FETs having gate widths equal to each other, and to the gates thereof a constant voltage is applied from the constant current source bias terminal V.sub.CS. Here, the FETs J12 and J14 are for strengthening the impedance conversion function of the source follower FETs J11 and J13 and are not necessarily required. Further, the gate widths of the FETs J11 to J14 are, for example, 30 to 50 .mu.m. The R11 and R12 designate resistors connected between the sources of the constant current source FETs J12 and J14 and the ground, respectively, and the resistance values thereof are, for example, 200 .OMEGA. to 1 k.OMEGA.. The Ca and Ra designate a capacitor and a resistor constituting the differential circuit 27a connected between the source node of the source follower FET J11 and the ground. The Rb and Cb designate a resistor and a capacitor constituting the integrating circuit 27b, and they are connected between the source node n3 of the source follower FET J13 and the ground. These resistors Ra and Rb are, for example, both 670 .OMEGA. when the target frequency is 950 MHz, and the capacitances are both, for example, 0.25 pF. The OUT1 is an output signal terminal and this is connected to the connection node of the capacitor Ca and the resistor Ra. The OUT2 is an output signal terminal connected to the connection node of the resistor Rb and the capacitor Cb. The Vi and V2 (=V1) are voltages of the nodes n1 and n3, respectively, and the Vout1 and Vout2 are voltages of the output terminals OUT1 and OUT, respectively.
A description is given of the operation.
A signal input from the signal input terminal IN is impedance converted by the source follower circuit 13a comprising FETs J11, J12, and the resistor R11 and the source follower circuit 13b comprising FETs J13 and J14, and the resistor R12, and they are output to the differential circuit 13c comprising the capacitor Ca and the resistor Ra and the integrating circuit 13d comprising the resistor Rb and the integrating circuit 13d.
FIG. 28 illustrates a vector diagram showing vectors V1, V2(=V1), Vout1, and Vout2 at frequency f=fO when the values of the resistor and the capacitor of the differential circuits 13c and the integrating circuit 13d are set so as to satisfy the following: EQU Ra=Rb=R, EQU Ca=Cb=C EQU fO=1/2.pi. RC
at the frequency fO.
In FIG. 28, .phi.1 represents the phase difference of V1 and Vout1 and .phi.2 represents the phase difference of V1 and Vout1.
At frequency f=fO, the differential circuit 27a has the same values for the absolute value for the voltage vector RaIa due to the voltage difference of the resistor Ra and the absolute value for the voltage vector Ia/j.omega.Ca due to the voltage difference of the capacitor Ca. Those voltage vectors are orthogonal and the triangle .DELTA.11 produced by both vectors and a sum vector of them is a right-angled isosceles triangle, and the output Vout1 advances in its phase .phi.01 by +45.degree. with relative to the phase of the input V1. The integrating circuit 27b has, as in the differential circuit 27a, the same values for the absolute value for the voltage vector RbIb due to the voltage difference of the resistor Rb and the absolute value for the voltage vector Ib/j.omega.Cb due to the voltage difference of the capacitor Cb which voltage. Those vectors are orthogonal and the triangle .DELTA.12 produced by both vectors and a sum vector is a right-angled isosceles triangle and the voltage Vout2 is retarded in its phase by 45.degree. with relative to the phase of the input V1. As a result, the phase difference (.theta.1+.theta.2) between those becomes 90.degree.. However, the amplitudes of the outputs Vout1 and Vout2 are reduced to lower values than the amplitude of the input V1 (=V2) due to the high pass characteristics of the differential circuit 27a and the low pass characteristics of the integrating circuit 27b. In addition, although the amplitudes of Vout1 and Vout2 are different from each other at a frequency other than f=fO, the phase difference therebetween (.theta.1 +.theta.2) is still maintained at 90.degree..
FIG. 29 is a diagram illustrating the amplitude characteristics of the output signals Vout1 and Vout2, as a function of the input frequency of the phase shifter of FIG. 27. FIG. 29 shows that the frequency at which the amplitudes of the Vout1 and Vout2 become equal to each other is only f=fO due to the high pass characteristics of the differential circuit and the low pass characteristics of the integrating circuits.
FIG. 30 shows the vector diagrams of V1 and V2(=V1), Vout1, Vout2 when the resistance values Ra (Rb) constituting the phase shifter in the circuit of FIG. 27 are increased to a value a little larger than the design value R, or when the capacitance value Ca(=Cb) of the capacitor is increased to a value a little larger than the design value C.
In FIG. 30, .theta.1 designates a phase difference between V1 and Vout1, and .theta.2 designates a phase difference between V1 and Vout1.
From FIG. 30, the angle .theta.1 is produced by Vout1 when V1 is small while the angle .theta.2 is produced by Vout2 when V2 is large, and the amplitudes of the Vout1 and Vout2 are different at f=fO while the sum of the phase difference between them, i.e., .theta.1+.theta.2, is kept at 90.degree..
The reason therefor is because the absolute value of the voltage vector RaIa for the resistor Ra constituting the differential circuit 27a and the absolute value of the voltage vector RbIb for the resistor Rb constituting the integrating circuit 27b are equal to each other, and the absolute value of the voltage vector Ia/j.omega.Ca for the capacitor constituting the differential circuit 27a and the absolute value of the voltage vector Ib/j.omega.Cb for the capacitor constituting the integrating circuit 27b are equal to each other because Ra=Rb=R, Ca=Cb=C on an assumption that V1=V2. The right-angled triangle .DELTA.11 constituted by the voltage vector RaIa, the voltage vector Ia/j.omega.Cb, and the voltage vector V1, and the right-angled triangle constituted by the voltage vector RbIb, the voltage vector Ib/j.omega.Cb, and the voltage vector V2 become congruent, and as a result, the angle .phi.1 produced by the voltage vector Ia/j.omega.Ca and the voltage vector V1, and the angle .theta.2 produced by the voltage vector Ib/j.omega.Cb and the voltage vector V2 are equal to each other. The angle .phi.32 produced by the voltage vector RbIb and the voltage vector V2 and the angle .phi.1 produced by the voltage vector RaIa and the voltage vector V1 are equal to each other, resulting in that the angle .theta.1+.theta.2 becomes necessarily 90.degree..
Therefore, this type of phase shifter can be said to have directionality over a wide range and is also resistant to variations in the elements.
In addition, as a conventional phase shifter that can maintain the phase difference between the orthogonal components while employing resistors and capacitors, there is a quadrature modulator disclosed in Japanese Published Patent Application Hei.2-127844, as one other than those illustrated in FIGS. 25 and 27.
FIG. 31 shows a construction of this quadrature modulator. In FIG. 31, reference numeral 311 designates a carrier wave input terminal, reference numeral 312 designates a first mixer for modulating a same phase component, reference numeral 313 designates a second mixer for modulating a quadrature component. The output of the first mixer 312 is connected to the modulation output terminal 316 via the resistive two-terminal circuitry 314. In addition, the output terminal of the second mixer 313 is connected to the modulation wave output terminal 316 via the capacitive two-terminal circuitry 315.
Next, the operation of this quadrature modulator will be described with reference to FIG. 32. First of all, suppose that the carrier wave which is input to the carrier wave input terminal 311 is V1=exp(j.omega.t), the base band signal which is input to the first mixer 312 is VI, and the base band signal which is input to the second mixer 313 is VQ. The output VIo of the first mixer 312 and the output VQo of second mixer 313 are respectively represented as follows: EQU ViO=VI.multidot.V1=VI.multidot.exp(j.omega.t) EQU VQo=VQ.multidot.V1=VQ.multidot.exp(j.omega.t)
In addition, the modulation wave output Vo(t) output from the modulated wave output terminal 316 is represented by the following formula if the resistance value of the resistive two-terminal circuitry 314 is R, the capacitance of the capacitive two-terminal circuitry 315 is C, and the output impedances of the first mixer 312 and the second mixer 313 are sufficiently low; EQU Vo=a1.multidot.V1+a2.multidot.VQ
here
a1=1/ (1+j.omega.CR), PA1 a2=j.omega.CR/ (1+j.omega.CR), PA1 a1=A1.multidot.exp(j.phi.1), PA1 a2=exp(j.phi.2) PA1 A1=1/ (1+(.omega.CR).sup.1/2), PA1 A2=.omega.CR/(1+(.omega.CR).sup.2).sup.1/2 PA1 .phi.1=tan.sup.-1 (-.omega.R), PA1 .phi.2=tan.sup.-1 (1/.omega.CR)
and if these a1 and a2 are expressed in phases, then
here,
The phasers of a1 and a2 move on the circle of diameter 1 as shown in FIG. 32. Then, the phase difference .DELTA..phi. between .phi.1 and .phi.2 becomes, employing a relation of EQU (a2/a1)=(A2/A1).multidot.exp(j(.phi.2-.phi.1))
as follows: ##EQU1## and, irregardless of the values of .omega., C, and R, it becomes 90.degree.. Accordingly, the phase difference between the same phase component (a1.multidot.V1) and the orthogonal component (a2.multidot.VQ) in the above-described voltage Vo=a1.multidot.V1+a2.multidot.VQ is also kept at 90.degree..
While in this circuit the phase difference between the same phase component and the orthogonal component is kept at 90.degree. independent of the value of the carrier wave frequency and the values of the circuit elements, the amplitude synthesization ratio K between the same phase component and the orthogonal phase component becomes EQU K=A2/A1=.omega.CR
and, it becomes the equi-amplitude synthesization when .omega.CR= 1.
FIG. 33 shows a phase shifter in which an FET 341 is provided in parallel with the resistor 342 as the resistive two-terminal circuitry 340, so as to enable the equi-amplitude synthesization, and the applied voltage of the amplitude synthesization ratio control terminal 343 which is connected to the gate thereof to be adjusted, whereby the amplitude synthesization ratio can be adjusted by simply employing the quadrature modulator.
FIG. 34 shows another phase shifter in which a diode 351 is connected in parallel with the condenser 352 as a capacitive two-terminal circuitry 350, so as to enable the equi-amplitude synthesization, and the cathode of the diode 351 is grounded via the choke coil 353. The applied voltage of the amplitude synthesization ratio control terminal 355 connected via the choke coil 354 to the anode of the diode 351 is adjusted, whereby the amplitude synthesization ratio can be adjusted by simply employing the quadrature modulator.
However, these prior art quadrature modulators shown in FIGS. 31 and 34 are not those used in a construction in which the input signal is initially separated into the components having phase differences of 0.degree. and 90.degree. by the 90.degree. power splitter 361, and the respective signals are amplified by the differential amplifiers 362 and 363 and modulated by the I channel double balanced mixer 364 and the Q channel double balanced mixer 365. These are synthesized by the 0.degree. synthesizer 366 and then amplified by the buffer amplifier 367 to be output. To the contrary, these quadrature modulators are applied to a 90.degree. synthesizer of a quadrature modulator in a construction in which a local oscillator input is amplified by a single differential amplifier 371, the modulated outputs are synthesized with those signals having a 90.degree. phase difference therebetween by the 90.degree. synthesizer 374, and amplified by the buffer amplifier 375, because two differential amplifiers are required in the construction of FIG. 35(a). Thus, the structures of these quadrature modulators in FIGS. 31 and 34 are clearly different from those shown in FIGS. 25 and 27 which are 90.degree. phase shifters in which the quadrature modulation signal is separated firstly by the 90.degree. phase shifter and is modulated by a mixer.
In the quadrature modulator of FIG. 35(b), there would occur an amplitude difference in the 90.degree. synthesizer at the last stage, and if no adjusting circuit is employed, this amplitude error cannot be solved. Therefore, the circuit of FIG. 31 would necessarily cause a problem in yield when it is constituted in the circuit construction as it is, and in order to avoid this, a circuit as shown in FIGS. 33 and 34 is required.
As a quadrature modulator that aims at dispensing with adjustments at the microwave band, Japanese Published Patent Application Hei.3-258056 discloses a non-adjustment quadrature modulator requiring no adjustment for quadrature PSK.
FIG. 36 shows a construction of this prior art non-adjustment modulator for quadrature PSK. Reference numeral 381 designates a local oscillator provided at outside, reference numeral 382 designates an input side EX-OR circuit which receives the I signal and the output of the local oscillator, reference numeral 383 designates a D flip-flop as a two frequency divider to which the output of the input side EX-OR circuit is input as a clock. An output signal, Q, is fed back to its D input, a signal which is obtained by two frequency divisions is output. Reference numeral 384 designates an output side EX-OR circuit which receives the Q signal and the output of the two frequency divider 384 as two inputs.
Next, a description will be given of the operation with reference to FIGS. 37(a)-37(d). The input side EX-OR circuit 382 operates as non-inverting for the output signal (1) from the local oscillator 381 when the input I=L, and operates as inverting for the signal (1) when the input signal I=H.
FIG. 37(a) shows where the state of I=L and Q=L; the output signal (1) of the local oscillator 381 which is input to the EX-OR circuit 382 as the input side gate is input as shown by (2), as a clock C of the two-divider circuit 383, remaining non-inverted. The two divider circuit 383 outputs the data of the D input at every rising of the clock C from the regular output terminal Q, and therefore, it outputs IF modulated wave as shown by (4), by dividing the input of the clock input terminal C by two, as shown by (3).
FIG. 37(b) shows where the state of I=H and Q=L; FIG. 37(d) shows where the state of I=H and Q=H, and FIG. 37(c) shows where the state of I=L and Q=H, the phases are sequentially shifted by 90.degree. at prescribed IF output as shown by the output of IF modulation wave of (4), and thus a modulator of non-adjustment for four phase PSK is realized.
However, the circuit of FIG. 36 is fundamentally different from the circuits of FIGS. 25 and 27 and also the operation frequency is limited by the flip-flop, and therefore, there arises a problem that some device is required in constructing a circuit for an actual mobile communication apparatus.
In this way, conventionally, 0.degree./90.degree. phase shifters appropriate for circuit integration which can be constituted only by resistors, capacitors, and transistors are limited to those utilizing the all-band pass circuit as shown in FIG. 25, or those which, using differential circuits and integrating circuits and utilizing the phase difference of the high pass filter characteristics and the low pass filter characteristics, separates the signals to those having phases of 0.degree. and 90.degree. phases.
However, in the circuits of FIG. 25 and 27 two current paths for output voltages orthogonal to each other are provided. When an adjustment circuit is provided only in one of the current paths so as to adjust element variations of the resistors and capacitors, influences by providing this adjustment circuit other current paths are affected, and it is required to provide similar adjustment circuits so as to cancel these influences, thereby resulting in difficulty in maintaining the orthogonality of the two output signals.